Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs

Degradation of lithographic pattern fidelity is a major cause of yield loss in VLSI manufacturing. A general methodology for full-chip analysis and improvement of yield loss due to lithographic effects is proposed. The approach is based on: a) extraction of pattern fidelity statistics using a full-chip layout engine, b) full-chip Optical Proximity Correction (OPC) to improve pattern reproduction, and c) estimation of yield losses due to line variability, using transistor sensitivity to pattern registration obtained from physical transistor modeling. As a result, yield estimates related to either pattern reproduction fidelity or transistor parametric data variations (such as leakage or drive current) are generated. The method is efficient and well suited for application to modern VLSI designs of memory or logic devices. Introduction Within-chip variability of critical features such as poly lines due to limitations of manufacturing processes is a major cause of device variability and product yield loss. A significant fraction of this variability is a deterministic function of local layout patterns and properties of the manufacturing processes (lithography, etch, etc.). In particular, optical proximity effects on the poly layer can degrade transistor parameters or even lead to catastrophic failures such as shorts or opens. Gate length variability is the main source of circuit-level variation and a major performance and yield limiter. Sensitivity of transistor performance to gate CD is a strong function of transistor architecture and, thus, the front-end manufacturing process. Reducing circuit-level variability can be achieved at two levels: Fig. 1. Schematic representation of design phase and manufacturing phase yield optimization. Design Manufacturing Mask Making OPC Process Improvement Lyout LE LW Vth Idsat Ioff Improved LE,LW Control Improved MOSFET Control Pduct Y eld Process Improvement Process Improvement ... Fab 1